Tenure Track Assistant Professor · RIT

Sathwika
Bavikadi

Department of Computer Engineering
Rochester Institute of Technology, New York
sxbeec at rit dot edu

My research focuses on the intersection of machine learning and hardware accelerator design, with an emphasis on building customized computing architectures and programming models optimized for domain-specific applications such as healthcare, transportation, security, IoT, and artificial intelligence.

I completed my PhD at George Mason University and previously worked as a Baseband Developer at Ericsson (Sweden). MS from Blekinge Institute of Technology, Sweden. Bachelor's from Jawaharlal Nehru Technological University, Hyderabad.

15+Publications
1Granted Patent
Sathwika Bavikadi

Research Interests

By addressing key challenges in memory management, performance optimization, energy efficiency, and system usability, my work makes intelligent computing more accessible across a wide range of real-world scenarios.

🧠

Memory-Centric AI

Co-designing algorithms and architectures that move compute into/near memory for low-latency, low-energy learning and inference.

Processing-in-MemoryProcessing-near-MemoryLUT-based Compute

Efficient AI on Device

Hardware-efficient ML methods. Sparse, quantization, KV cache management for edge hardware and heterogeneous SoCs.

QuantizationEdge AILLM
🔧

Algorithm–Architecture Co-design

Scheduling, dataflow, and partitioning strategies that align model structure with memory hierarchies and bandwidth constraints and heterogeneous architectures.

Dataflow OptimizationHardware MappingDNN Acceleration
Open Positions

Join My Intelligent Computing Research Lab

My research currently has openings for PhD, MS, and BS/MS students. Candidates need basic knowledge in one or more of the following areas:

Digital System Design VLSI Machine Learning
Apply via Form sxbeec@rit.edu

Recent News

March 2026 GrantReceived the CHAI FaSe Seed Fund from Center for Human-aware AI at Rochester Institute of Technology.
Aug 2025 Paper'Enhancing Few-Shot Image Captioning with Discrete Region-Token Alignment and Retrieval Augmented Learning' accepted at MIPR 2025.
Jul 2025 Paper'3D-PLANE: A 3D-stacked DRAM-based Programmable SLM Accelerator' accepted at GLSVLSI 2025.
Jun 2025 Paper'Adora: An Arithmetic and Dynamic Operation Reconfigurable Accelerator' accepted as Poster at DAC 2025.
May 2025 AwardReceived the ECE Outstanding Academic Achievement Award from George Mason University.
May 2025 AwardReceived the Mason Innovation Award from George Mason University.
Jan 2025 GrantReceived the Grant Writers Boot Camp Seed Fund from Rochester Institute of Technology.
Sep 2024 TalkInvited talk at ESWEEK 2024 — LLM-PIM: Large Language Model Acceleration using Processing-In-Memory Architectures.
Aug 2024 Joined Rochester Institute of Technology as Tenure Track Assistant Professor in Computer Engineering.
Mar 2024 AwardSelected as NSF iREDEFINE Fellow by ECEDHA.
Oct 2023 PatentPatent "Look-up table containing processor-in-memory cluster" granted by the USPTO.

Publications

📄 Patent
Amlan Ganguly, Sai Manoj P.D., Mark Connolly, Purab Ranjan Sutradhar, Sathwika Bavikadi, Mark Allen Indovina
United States Patent and Trademark Office
📰 Journal Papers
Sathwika Bavikadi, Purab Ranjan Sutradhar, Mark Indovina, Amlan Ganguly, Sai Manoj P.D.
IEEE Transactions on Computer-Aided Design (TCAD), 2024
Purab Ranjan Sutradhar, Sathwika Bavikadi, Mark Indovina, Sai Manoj P.D., Amlan Ganguly
IEEE Transactions on Emerging Topics in Computing (TETC), 2023
Sathwika Bavikadi, Abhijitt Dhavlle, Amlan Ganguly, et al.
IEEE Design & Test, 2022
Purab Ranjan Sutradhar, Sathwika Bavikadi, et al.
IEEE Transactions on Parallel and Distributed Systems (TPDS), 2021
Purab Ranjan Sutradhar, Mark Connolly, Sathwika Bavikadi, et al.
IEEE Computer Architecture Letters (CAL), 2020
🏛 Conference Papers
Stefan Maczynski, Amlan Ganguly, Mark Indovina, Purab Sutradhar, Sai Manoj Pudukotai Dinakarrao, Sathwika Bavikadi
GLSVLSI 2025
Sathwika Bavikadi, Purab Ranjan Sutradhar, Jayanth Thangellamudi, Sai Manoj P.D.
GLSVLSI 2025
Sreenitha Kasarapu*, Sathwika Bavikadi*, Sai Manoj P.D.
VLSID 2024
Sathwika Bavikadi, Purab Ranjan Sutradhar, Amlan Ganguly, Sai Manoj P.D.
VLSID 2024
Sathwika Bavikadi, Purab Ranjan Sutradhar, Amlan Ganguly, Sai Manoj P.D.
ISQED 2023

Teaching

Fall CMPE 550 Computer Architecture
Spring CMPE 677 Machine Intelligence

Awards & Honors

2026
CHAI-FaSe Seed Fund — Rochester Institute of Technolog
2025
ECE Outstanding Academic Achievement Award — George Mason University
2025
Mason Innovation Award — George Mason University
2025
Grant Writers Boot Camp Award — Rochester Institute of Technology
2024
NSF iREDEFINE Fellow — ECEDHA
2024
Provost Doctoral Fellowship — George Mason University
2022–24
DAC Young Fellow Program (×3 selections)
2023
Dissertation Completion Grant — George Mason University
2023
DATE Young Fellow Program

Professional Service

Session Chair

  • GLSVLSI 2025
  • MIPR 2025

Program Committee

  • DAC 2025, 2026
  • ISQED 2025
  • ESWEEK 2025
  • GLSVLSI 2024, 2025, 2026
  • ISVLSI 2024
  • IGSC 2024
  • IEEE iSES 2024

Main Reviewer

  • TCAD 2023, 2024
  • TCAS-1 2023, 2024
  • ICCD 2022, 2024
  • ISCAS 2024
  • GLSVLSI 2024
  • SUSCOM 2023

Leadership

  • iREDEFINE Mentoring Hub (Since 2024)
  • IEEE Young Professional Micro-Mentoring (Since 2024)
  • IEEE Women in Engineering (Since 2020)
  • Women in HPC (Since 2021)