Department of Computer Engineering
Rochester Institute of Technology, New York
sxbeec at rit dot edu
My research focuses on the intersection of machine learning and hardware accelerator design, with an emphasis on building customized computing architectures and programming models optimized for domain-specific applications such as healthcare, transportation, security, IoT, and artificial intelligence.
I completed my PhD at George Mason University and previously worked as a Baseband Developer at Ericsson (Sweden). MS from Blekinge Institute of Technology, Sweden. Bachelor's from Jawaharlal Nehru Technological University, Hyderabad.
By addressing key challenges in memory management, performance optimization, energy efficiency, and system usability, my work makes intelligent computing more accessible across a wide range of real-world scenarios.
Co-designing algorithms and architectures that move compute into/near memory for low-latency, low-energy learning and inference.
Hardware-efficient ML methods. Sparse, quantization, KV cache management for edge hardware and heterogeneous SoCs.
Scheduling, dataflow, and partitioning strategies that align model structure with memory hierarchies and bandwidth constraints and heterogeneous architectures.