Sathwika Bavikadi

sxbeec at rit dot edu

I am a Tenure Track Assistant Professor in the Department of Computer Engineering at Rochester Institute of Technology (RIT) .

My major research interest is in "Machine learning for hardware accelerator design" in simple words, my work comprises creating customized computer architectures and programming for domain-specific applications such as healthcare, transportation, security, IoT, AI, and ML.

I completed my PhD in the Electrical and Computer Engineering Department at George Mason University (GMU) , Fairfax, Virginia. Under the guidance of Dr. Sai Manoj PD, Assistant Professor at GMU, funded by NSF, (Commonwealth Cyber Initiative) CCI and DARPA. My research work has culminated in a patent publication and numerous contributions to leading conferences and journals, including at various venues including TCAD, ISQED, GLSVLSI, TPDS, CAL, and ISCAS.

Before joining GMU, I worked as a PD Baseband Developer at Ericsson, Lund, Sweden. I got my Master's degree from Blekinge Institute of Technology (BTH), Sweden in Electrical Engineering emphasising Signal Processing. I did my Bachelors degree at Jawaharlal Nehru Technology University, Hyderabad, India.

Research Interests

I am passionate about Research and Development. I'm interested in Machine Learning, Tiny ML, In-Memory Computing, Computer Architecture, High-Performance Computing, Hardware Software Co-Design, IoT, Artificial Intelligence and Signal Processing.

Projects I worked on:

Machine learning on hardware accelerator design.
Hardware-software co-design on Processing-in-Memory systems.
Reconfigurable Processor-in-Memory design to handle multiple functionalities of ML algorithms.
Heterogeneous hardware accelerator design for handling humongous computational load.
Online Learning on PIM for Low power IoT applications.
Approximate Computing and Mixed Precision Implementation on Deep Neural Networks.

My future research vision:

Developing novel ML hardware architectures that meet the evolving demands of AI workloads.
Advancing research in heterogeneous computing, co-design of hardware and software, and energy-efficient accelerators.
Efficient Embedded AI acceleration, model compression, pruning, quantization, hardware-aware neural architecture search, on-device training and inference.
Neuromorphic computing-based Deep Neural Networks.
Exploring the Heterogeneous Quantum-CMOS Accelerators.

I am seeking motivated and technically strong PhD students, interns, and research assistants (both graduate and undergraduate) to join my lab. If you're interested, please fill out this form and shoot me an email.

News

September 2024 → Attending ESWEEK to present an invited talk in the workshop session titled LLM-PIM 2024: Large Language Model Acceleration using Processing-In-Memory Architectures.
August 2024 → Joining Rochester Institute of Technology (RIT) as a Tenure Track Assistant Professor in the Department of Computer Engineering.
June 2024 → Selected and Attended the Design Automation Conference (DAC) Young Fellowship Program (2024) to present my work in the poster session.
March 2024 → Selected as an NSF iREDEFINE Fellow by the Electrical and Computer Engineering Department Heads Association (ECEDHA), where I presented my research work
Feb 2024 → Presented my PHD work at George Mason University's ECE seminar .
Jan 2024 → Attended VLSID 2024, and presented 2 poster presentations on two of my accepted papers .
Jan 2024 → Invited to give a guest lecture at Indian Institute of Technology Hyderabad (IITH).
Dec 2023 → Got selected to receive 2024 Dissertation Completion grant from George Mason University.
Oct 2023 → Our patent application titled "Look-up table containing processor-in-memory cluster for data-intensive applications" is granted and published by United States Patent and Trademark Office.
Feb 2023 → Got selected for Design, Automation and Test in Europe Conference (DATE) 2023 Young fellow Program.
Oct 2022 → Our patent application is published by United States Patent and Trademark Office.
Feb 2022 → Got selected for 59th Design Automation Conference (DAC) Young fellow Program.
Nov 2021 → Selected and Attended 58th Design Automation Conference (DAC) Young fellow Program.
July 2021 → Presented my work at ICONS 2021 Doctoral Consortium.
May to August 2021 → Worked as a Visiting Researcher at University of Southern California (USC) Information Sciences Institute (ISI) under the supervision of Dr. Andrew Schmidt, Senior Computer Scientist / Research Lead, Computational Systems and Technology at USC-ISI.
Nov 2020 → Attended NeuralIPS 2020 Conference.
Oct 2020- 2021 → Helped the author while writing the book Machine Learning for Computer Scientists and Data Analysts from an Applied Perspective.

Selected Publications

Patents

Look-up table containing processor-in-memory cluster for data-intensive applications
Amlan Ganguly, Sai Manoj Pudukotai Dinakarrao, Mark Connolly, Purab Ranjan Sutradhar, Sathwika Bavikadi, Mark Allen Indovina
United States Patent and Trademark Office

Journal Papers

	ReApprox-PIM: Reconfigurable Approximate Look-Up-Table (LUT)-Based Processing-in-Memory (PIM) Machine Learning Accelerator Sathwika Bavikadi, Purab Ranjan Sutradhar, Mark Indovina, Amlan Ganguly, Sai Manoj Pudukotai Dinakarrao Keywords: Computer architecture, In-Memory Computations, Approximation, Look-up Table, Hardware acceleration 2024 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)
	3DL-PIM: A Look-up Table oriented Programmable Processing in Memory Architecture based on the 3-D Stacked Memory for Data-Intensive Applications Purab Ranjan Sutradhar, Sathwika Bavikadi, Mark Indovina, Sai Manoj Pudukotai Dinakarrao, Amlan Ganguly Keywords: Computer architecture, In-Memory Computations, Look-up Table, Parallel processing, Hardware acceleration 2023 IEEE Transactions on Emerging Topics in Computing (TETC)
	A Survey on Machine Learning Accelerators and Evolutionary Hardware Platforms Sathwika Bavikadi, Abhijitt Dhavlle, Amlan Ganguly, Anand Haridass, Hagar Hendy, Cory Merkel, Vijay Janapa Reddi, Purab Ranjan Sutradhar, Arun Joseph, Sai Manoj Pudukotai Dinakarrao Keywords: Field programmable gate arrays , Hardware , Machine learning , Computer architecture , Optimization , Neural networks , Graphics processing units , Machine learning , Artificial intelligence IEEE Design & Test 2022 paper \| bibtex
	Look-up-Table based Processing-in-Memory Architecture with Programmable Precision-Scaling for Deep Learning Applications Purab Ranjan Sutradhar, Sathwika Bavikadi, Mark Connolly, Savan Kumar Prajapati, Mark A Indovina, Sai Manoj Pudukotaidinakarrao, Amlan Ganguly Keywords: Computer architecture, Random access memory, Table lookup, Performance evaluation, Registers, Parallel processing, Optimization IEEE Transactions on Parallel and Distributed Systems 2021 (TPDS) paper \| bibtex \| video
	pPIM: A Programmable Processor-in-Memory Architecture With Precision-Scaling for Deep Learning Purab Ranjan Sutradhar, Mark Connolly, Sathwika Bavikadi, Sai Manoj Pudukotai Dinakarrao, Mark A. Indovina, Amlan Ganguly Keywords: Processing in memory, look up table, convolutional neural network,deep neural network,DRAM IEEE Computer Architecture Letters (CAL), July 2020 paper \| bibtex \| video

Conference Papers

	Energy Harvesting-assisted Ultra-Low-Power Processing-in-Memory Accelerator for ML Applications Sanket Shukla, Sathwika Bavikadi, Sai Manoj Pudukotai Dinakarrao Keywords: Computer architecture, In-Memory Computations, Look-up Table, Hardware acceleration 2024 Proceedings of the Great Lakes Symposium on VLSI (GLSVLSI)
	Reconfigurable Processing-in-Memory Architecture for Data-Intensive Applications Sathwika Bavikadi, Purab Ranjan Sutradhar, Amlan Ganguly, Sai Manoj Pudukotai Dinakarrao Keywords: Computer architecture, In-Memory Computations, Look-up Table, Hardware acceleration 2024 International Conference on VLSI Design (VLSID)
	Processing-in-Memory Architecture with Precision-Scaling for Malware Detection Sreenitha Kasarapu, Sathwika Bavikadi, Sai Manoj Pudukotai Dinakarrao Keywords: Computer architecture, In-Memory Computations, Look-up Table, Precision-Scaling, Malware Detection,Hardware acceleration 2024 International Conference on VLSI Design (VLSID)
	FlutPIM: A Look-up Table-based Processing in Memory Architecture with Floating-point computation Support for Deep Learning Applications Purab Ranjan Sutradhar, Sathwika Bavikadi, Mark Indovina, Sai Manoj Pudukotai Dinakarrao, Amlan Ganguly Keywords: Computer architecture, In-Memory Computations, Look-up Table, Parallel processing, Hardware acceleration Proceedings of the Great Lakes Symposium on VLSI 2023 (GLSVLSI) paper \| bibtex
	Heterogeneous Multi-Functional Look-Up-Table-based Processing-in-Memory Architecture for Deep Learning Acceleration Sathwika Bavikadi, Purab Ranjan Sutradhar, Amlan Ganguly, Sai Manoj Pudukotai Dinakarrao Keywords: Multi-functional, Look-up-table, Machine Learning, Convolutional Neural Networks, In Memory Computations, Computer architecture, Processing-in-Memory, Hardware acceleration. The 2023 International Symposium on Quality Electronic Design (ISQED) paper \| bibtex
	Reconfigurable FET Approximate Computing-based Accelerator for Deep Learning Applications Raghul Saravanan, Sathwika Bavikadi, Sai Manoj Pudukotai Dinakarrao Keywords: Reconfigurable FET, Machine Learning, Convolutional Neural Networks, Approximate Computations, Computer architecture, Hardware acceleration. 2023 IEEE International Symposium on Circuits and Systems (ISCAS)
	Coarse-Grained High-Speed Reconfigurable Array-Based Approximate Accelerator for Deep Learning Applications Katherine Nicole Mercado Rejas, Sathwika Bavikadi, Sai Manoj Pudukotai Dinakarrao Keywords: Approximate Computing, Machine Learning, Convolutional Neural Networks, Computer architecture, Hardware acceleration. The 57th Conference on Information Sciences and Systems (CISS) paper \| bibtex
	Accelerating Adversarial Attack using Process-in-Memory Architecture Shiyi Liu, Sathwika Bavikadi, Tanmoy Sen, Haiying Shen, Purab Ranjan Sutradhar, Amlan Ganguly, Sai Manoj Pudukotai Dinakarrao and Brian Smith Keywords: Adversarial Attacks, Real-time systems, Computer architecture, Processing-in-Memory, Hardware acceleration. The 18th International Conference on Mobility, Sensing and Networking (MSN 2022) paper \| bibtex
	POLAR: Performance-aware On-device Learning Capable Programmable Processing-in-Memory Architecture for Low-Power ML Applications Sathwika Bavikadi, Purab Ranjan Sutradhar, Amlan Ganguly, Sai Manoj Pudukotai Dinakarrao Keywords: Generative adversarial networks, Real-time systems, Computer architecture, Performance evaluation, Parallel processing, Hardware acceleration Euromicro Conference on Digital System Design 2022 paper \| bibtex
	uPIM: Performance-aware Online Learning Capable Processing-in-Memory Sathwika Bavikadi, Purab Ranjan Sutradhar, Amlan Ganguly, Sai Manoj Pudukotai Dinakarrao Keywords: Generative adversarial networks, Real-time systems, Computer architecture, Performance evaluation, Parallel processing, Hardware acceleration 2021 IEEE 3rd International Conference on Artificial Intelligence Circuits and Systems (AICAS) paper \| bibtex
	A Review of In-Memory Computing Architectures for Machine Learning Applications Sathwika Bavikadi, Purab Ranjan Sutradhar, Khaled N Khasawneh, Amlan Ganguly, Sai Manoj Pudukotai Dinakarrao, Keywords: Processing in memory, look up table, convolutional neural network, deep neural network, Proceedings of the 2020 on Great Lakes Symposium on VLSI (GLSVLSI), September 2020 paper \| bibtex \| video

Awards and Recognition

[2024] Received Provost Doctoral Fellowship from GMU
[2024] Selected as an NSF iREDEFINE Fellow by the Electrical and Computer Engineering Department Heads Association (ECEDHA)
[2024] Selected for DAC young fellow program.
[2024] Selected for DATE young fellow program.
[2022] Selected for DAC young fellow program.
[2021] Selected for DAC young fellow program.

Teaching

Course at RIT:

[Spring 2024] CMPE 677 Machine Intelligence

During my PhD at GMU I served as a grader, Instructor, and TA for various courses at the undergraduate and graduate levels from Spring 2020 to Spring 2022 at GMU.

Graduate level courses: (capacity of 30-45 students/class)

Learning from Data, Big Data Technologies, Computer Architecture, Digital System Design with VHDL and VLSI Design for ASICs.

Undergrad level courses: (capacity of ∼75-120 students/class)

Digital Electronics, Electric Circuit Analysis, Computer Networking Protocols, FPGA and ASIC Design with VHDL.

Invited Talks

[2024] Presented an invited talk at the IEEE ESWEEK conference in a workshop session titled LLM-PIM: Large Language Model Acceleration using Processing-In-Memory Architectures.
[2024] Indian Institute of Technology, Hyderabad, India (IITH).
[2024] Poster Presentation at Design Automation Conference(DAC) Conference.
[2024] Poster Presentation at Electrical and Computer Engineering Department Heads Association (ECEDHA) Conference.
[2023] Sustainable Research Pathways (SRP) Workshop.
[2021] International Conference on Neuromorphic Systems (ICONS) Doctoral Consortium.

Professional Service

I commit 1~2 hours every week to offer guidance, suggestions, and mentorship to students from underrepresented groups or anyone in need. If you're interested, please fill out this form.

Served as a Program Committiee for: GLSVLSI '24, ISVLSI'24, IGSC'24, IEEE iSES'24.

Served as a Main Reviewer for:

Journal Reviewer: SUSCOM '23, Integration '23, TCAD ('23,'24), TCAS-1 ('23,'24).
Conference Reviewer: ICCD ('22,'24), SUSCOM '23, Integration '23, TCAD ('23,'24), TCAS-1 ('23,'24), ISCAS '24, GLSVLSI '24, ISVLSI'24.

Served as a Secondary Reviewer for: ESWEEK CASES ('22,'23), TCAD '23, ISCAS '22, HPCA '22, ICCAD ('21,'22), DAC '22, GLSVLSI ('20,'21), IEEE ACCESS '21.

Leadership Experience :

Member of iREDEFINE Mentoring Hub (Since 2024)
Member of IEE Young Professional Micro-Mentoring Program (Since 2024)
Member of IEEE Women in Engineering (Since 2020)
Member of Women in High-Performance Computing (Since 2021)
President of a Yoga Group at GMU (2020-2024)
Lead driver for Ericsdotter (women’s network in Ericsson) (2018-2019)
Led a Student Innovative cell at BTH (2017)

"Learning is paramount and everything else comes later."